Thanks to the increasing processing power of integrated circuits the goal of achieving true multimedia communication is closer to becoming a reality. One major aspect of multimedia communication is providing a visual link for users. A key component needed to establish this visual connection is the video camera. To facilitate widespread utilization of visual communication, the video cameras that go with desktop PCs or other multimedia communication devices must be inexpensive, lightweight and power-efficient. One factor in the cost of a video camera is the degree of integration between the image capturing device and the associated application-specific image processing circuitry (costs are reduced when both are integrated on the same chip).
Traditionally, solid state based cameras are realized using charge-coupled devices (CCDs) as image capturing devices. Although high quality consumer products such as camcorders have been successfully built using CCDs, CCD technology is not compatible with standard DC processes. As a result, CCD-based cameras are relatively expensive. In addition, CCDs use high voltage clock signals, implying correspondingly high power dissipation levels. Therefore, there is much interest in building single chip cameras using standard CMOS processes, which would promote integration and low power consumption.
The prior art includes several types of single-chip, CMOS pixel sensor arrays. The principal difference between these array types is in the structure of their constituent photo cells. Generally, each array comprises a regular arrangement of photo cells, each of which provides a signal correlated to the amount of light failing on that cell. In color arrays, groups of three adjacent cells responsive to different primary wavelengths of light provide three respective signals that are combined to form a single color pixel. On monochromatic arrays, each cell generates a signal that alone forms a corresponding pixel.
Prior art CMOS sensor arrays have been implemented using photodiodes or photogates as light sensing elements/photocells. Operations of three prior art sensor arrays based on photogates or photodiodes are now described and their respective advantages and disadvantages are highlighted.
FIG. 1 depicts a generic realization of a photogate-based photocell 108 that can be used in an active pixel sensor. Each cell 108 has a photogate device PG, a storage node/capacitor SG, a transistor for charge transfer MT, a transistor to reset storage node potential MS, a row select transistor MR and a source follower transistor MSF. During an integration period in which the cell 108 collects photons, a positive potential is applied to the gate of the photogate device PG so that the region 122 of the p-type substrate 120 immediately under the gate is depleted of majority carriers. Photons that penetrate into the silicon during the integration period generate electron-hole pairs if they are suitably energetic. For those pairs that are generated in the carrier-depleted region 122, the electric field set up across the photogate device PG tends to sweep the electrons towards the oxide-silicon interface 124 and the holes to the substrate 120. The depleted junction area 122 also serves as a collection region for electrons generated in the substrate.
As the integration time progresses more electrons are created and accumulated at the oxide-silicon interface 124. During the integration period the signals XFER and RS are maintained at a low enough level that the transistors MT and MS are kept off. Towards the end of the integration period, while the gate PG is still at a positive potential, the device MS is pulsed on momentary by applying a high RS signal. This action returns the storage node SG to a potential that is about one threshold voltage below the supply voltage VDD. This "reset" value is read and stored by a readout circuit that includes the source follower transistor MSF and the row select transistor MR. During the readout operation, the ROW signal is asserted when it is time to read the sensor array row that includes the cell. When the ROW signal is asserted the OUTPUT signal is determined by the gate voltage of the source follower transistor MSF, which is in turn determined by the voltage across the storage node SG.
Following the reading of the reset value, the integration period is ended by returning the gate PG to a low potential value, for example VSS (typically at ground), and, at the same time, turning on the transistor MT by applying a positive XFER signal. These actions create a path connecting the storage node SG and the photogate region PG. Accumulated electrons will tend to flow from the gate PG towards the storage node SG, which has a higher potential. A voltage drop occurs at the storage node whose final value depends on the amount of electrons accumulated during the integration period and the capacitance at the storage node. This voltage is read by the readout circuit that includes the source follower transistor MSF and the row readout transistor MR as described above. The difference between this voltage and the previously stored "reset" value represents the total amount of light falling onto the sensor. This operation is repeated periodically for each pixel cell so that a time sampled scene is obtained.
The advantage of photogate-based cells is that a high charge-to-voltage conversion gain can be realized because of the low storage node SG capacitance. This in turn gives good low light performance because the noise contributions from the reset switch MS and the read amplifier MR are small due the cell's high conversion gain. A noise floor of 20 electrons to 40 electrons can be realized with this cell structure. A disadvantage with photogate devices is that they have lower quantum efficiency because light has to go through the polysilicon gate before creating electron-hole pairs. This degradation is particularly pronounced at smaller wavelengths and thus gives relatively poor blue color response.
FIG. 2 depicts a generic realization of a photodiode-based photocell 138 that can be used in an active pixel sensor array. The cell 138 consists of a reverse-biased junction diode PD acting as a light sensor, a transistor MS to reset a storage node ST and the diode potential, a source follower buffer transistor MSF and a row select transistor MR. Initially, a positive RS signal is applied to the gate of the transistor MS, which turns on as a result and resets the voltage across the diode PD to some preset value. The measurement of light energy is accomplished by turning off the transistor MS and letting the voltage across the diode PD discharge in response to the light energy failing on it. The amount of voltage change across the diode PD is proportional to the illumination level of the light to which it is exposed. After a predetermined integration time the voltage level across the diode PD is sampled at the OUTPUT node. The actual signal due to the amount of illumination falling on the cell 138 during the integration period is the difference between the voltage measured at the end of the integration period and the output voltage obtained after turning on the reset transistor MS to reset the diode voltage to the preset value. These steps essentially remove the uncertainty of the voltage drop across the source follower MSF in the actual signal. These steps also reduce the 1/f noise contribution.
1/f noise is noise which has most of its energy concentrated at lower frequencies. Its power spectral density has a form like K/f, hence the name, 1/f noise. It is also called flicker noise. The cause of 1/f noise in MOS devices is generally believed to be impurities and contamination at the gate oxide/silicon interface. Thus, 1/f noise originates from the devices employed in the MOS pixel sensor arrays.
An additional transistor can be inserted between the diode PD and the gate of transistor MSF to facilitate easier implementation of a shutter period control, wherein the shutter period is the photodiode integration time for each image frame. Using another transistor allows the shutter period to be controlled independently of the RS signal control.
The main disadvantage of the cell 138 is that its electron-to-voltage conversion gain is lower than that of photogate-based cells. This makes the relative contribution of noise due to the amplifier buffer MSF and the reset switch MS more significant at low light levels than in photogate-based cells. This effectively raises the cell's noise floor and degrades its performance relative to photogate-based cells at low levels of illumination. However, when the illumination level increases to the point where the contribution of the shot noise (statistical fluctuations in the current) becomes significant or dominant, the signal to noise ratio (SNR) for the photodiode cell 138 is higher than that of the photogate based cell 108. This is due to the fact that shot noise dominated SNR is proportional to the square root of the number of electrons accumulated and the photodiode has a higher quantum efficiency than photogate devices (i.e., the photodiode accumulates more electrons for a given level of light). In fact, the input dynamic range for the photodiode cell is the similar to that of the photogate based cell (where input dynamic range is defined as the range of input illumination levels to which the image sensor can respond within a fixed integration time). The only difference is that the dynamic range for photogate devices is from low illumination to moderately bright illumination levels and for photodiode devices is from moderate illumination to very bright illumination levels. Therefore, whether a photogate or photodiode cell should be used depends on the intended sensor array applications and the expected operating environment.
A third photocell design is the passive pixel cell. FIG. 3 shows one column of an active sensor array based on passive pixel cells 168. A passive pixel cell 168 has a very simple structure consisting of a photodiode PD with an associated capacitance C.sub.d and a transistor switch MR. The photodiodes from different rows are connected to a common column bus 170 through the switches MR1, MR2, . . . , MRx that are located inside each cell. Each column bus is coupled to the input of a charge amplifier AMP, which provides a signal V.sub.o that indicates the level of illumination collected by a one of the photodiodes PD. Before reading any of the photodiodes PD the amplifier is first reset and the resulting value V.sub.o stored. The photodiode PD of a selected row is then connected to the input of the charge amplifier AMP by closing the corresponding switch MR. Under ideal conditions the charge accumulated on the photodiode PD during the integration period is transferred onto the integration capacitor having capacitance C.sub.f. This results in a change in the output voltage, V.sub.o, with a value given by ##EQU1## where V.sub.d represents the voltage discharged across the photodiode PD during the integration period. By choosing ##EQU2## greater than one, a high electron-to-voltage conversion gain can be realized at the output V.sub.o. In principle, the noise contribution of the reset switch M.sub.reset can be made negligible, in which case the main source of noise is the amplifier AMP. Real devices built with this type of pixel cell reportedly perform worse than the ideal case and their overall performance seems to be worse than the photogate based cells.
The following are some of the practical issues that need to be addressed in passive pixel cells.
Mismatches in charge injection and clock feedthrough due to the switches MR can affect fixed pattern noise (FPN) performance significantly. Further, in order to reduce the amount of signal charge loss to the column bus capacitance C.sub.bus the amplifier AMP has a very high minimum gain requirement. For example, for an overall voltage gain ##EQU3## of two, where V.sub.d is the voltage drop across one of the photodiodes PD, and a typical ##EQU4## ratio of 40 to 50, an amplifier gain of 80 to 100 is needed to merely make the effective capacitance of the integration capacitor at the input of the amplifier AMP equal to C.sub.bus. To further reduce the effect of C.sub.bus on signal loss, an amplifier gain of a few hundred to a thousand is needed. Coupled with the large C.sub.bus at the input of the amplifier AMP, this can lead to stability problems. All of these issues complicate the overall design. In addition, increasing the resolution, and thus the size of array, increases the ##EQU5## ratio further, which only exacerbates the gain and stability requirement. Therefore, this topology does not scale well with technology.